1. Field of the Invention
The present invention relates to a pattern forming method and an article manufacturing method.
2. Description of the Related Art
With an increase in miniaturization of semiconductor devices as articles, the fidelity of transferring a design pattern on a wafer has been reducing year by year, resulting in difficulty in coping with such a circumstance using previous two-dimensional shape pattern formation. In order to cope with such a circumstance, the 1D layout for constituting a design pattern only by using a linear pattern extending in one direction is employed. There is a technical document describing a pattern forming method according to the 1D layout (M. Smayling, and V. Axelrad “32 nm and below Logic Patterning using Optimized Illumination and Double Patterning”, Proc. of SPIE, Vol. 7274, 72740K-1-72740K-3, 2009.). FIG. 14 is a schematic plan view illustrating the shapes of an L/S (line-and-space) pattern 100 and a cut pattern (resist pattern) 102 which are formed by the pattern forming method according to the 1D layout. According to the pattern forming method, the L/S pattern 100 is firstly formed on the entire chip. Then, a pattern 101 in which the L/S pattern 100 is combined with the resist pattern 102 can be formed in the underlying layer such that some of space portions are cut by using a plurality of resist patterns 102.
A lithography apparatus represented by an exposure apparatus is used for forming such a pattern. The exposure apparatus is an apparatus that transfers a pattern of an original (reticle, mask, or the like) onto a photosensitive substrate (e.g., wafer or the like where the surface thereof is coated with a resist layer) via a projection optical system in a lithography process included in manufacturing steps for a semiconductor device, a liquid crystal display device, and the like. Upon forming an L/S pattern, the exposure apparatus transfers an image of a pattern formed on an original onto a wafer in a resolvable range. In particular, in the current exposure apparatus, given that a process coefficient is 0.25, a wavelength of ArF laser as the light source is 193 nm, and a maximum NA (numerical aperture) is 1.35, the limit resolution of the L/S pattern is 36 nm L/S, i.e., the product of 0.25 and (193/1.35). However, a size equal to or less than 30 nm L/S is required in order to cope with the manufacture of current front-line devices. Accordingly, for example, a pattern forming method including a step of forming a side wall consisting of an oxide film and a step of removing the side wall has been employed in order to form an L/S pattern finer than 36 nm L/S in recent years.
The aforementioned pattern forming method utilizing a side wall may be mainly applied to a gate step and a metal step in the device manufacturing steps. Among them, in the metal step of the conventional pattern forming method, the cut pattern 101 is a remaining pattern. Here, the 1D layout may be regularly employed in 20 nm node or further beyond. For example, the pattern size in 16 nm node is 32×50 nm. At this time, the thickness of the resist film is set in the range of from 50 to 100 nm. However, in this state, the depth of the pattern to the line width of the pattern (the pattern aspect ratio) exceeds 1 and the installation area (formation area) is narrower than the conventional pattern, so that the already-formed resist pattern may be peeled off upon development.